1. Field of the Invention
This invention is generally related to semiconductor memories and, more particularly, to dynamic random access memories (DRAMs) in which the configuration (or number) of output data buffers can be varied.
2. Description of the Related Art
In the related art, dynamic random access memories with n-channel metal oxide semiconductor (NMOS) output buffers can be provided with a variable number of output buffers. The output buffer supply circuit providing the voltage, generally referred to as Vpp, has a single sized pumping capacitor for both a one output buffer and a four output buffer configuration. The NMOS output buffer provides both the pull-up function and the pull-down function of the data bus external to the integrated circuit. When the pull-up transistor (133 in FIG. 1) is required to drive a high voltage level to the data bus, the gate terminal of the pull-up transistor must have a booted voltage applied thereto. This booted voltage is referred to as the Vpp voltage and is generated within the dynamic random access memory unit. Using a bond pad option during the fabrication process, the dynamic random access memory can be configured as a one buffer memory unit or as a four buffer memory unit.
Referring to FIG. 1, a schematic diagram of a buffer circuit which is used in conjunction with a buffer supply circuit is shown. The WOEN.sub.-- signal is coupled to first terminal and a gate terminal of n-channel transistor 103, and to a gate terminal of n-channel transistor 109. The WOEN signal is coupled to a gate terminal of n-channel transistor 101. The WOE3.sub.-- signal is coupled to a first terminal of transistor 101 and to a gate terminal of transistor 111. A first terminal of transistor 109 is coupled to ground. A first terminal of transistor 111 is coupled to ground, while a second terminal of transistor 111 is coupled to a second terminal of transistor 109, a first terminal of p-channel transistor 107, a gate terminal of p-channel 105, a gate terminal of p-channel transistor 123, a gate terminal of n-channel transistor 124, a gate terminal of p-channel transistor 125 and a gate terminal of n-channel transistor 127. A second terminal of transistor 101 is coupled to a second terminal of transistor 103, a first terminal of transistor 105, and to the gate terminal of transistor 107. The WDLAT signal is coupled to a first terminal of CMOS pass gate transistor 117 and to an input of inverter amplifier 115. The output terminal of inverter 115 is coupled to a second terminal of pass gate transistor 117. The IOMUX3 signal is coupled to an output terminal of pass gate transistor 117, to an input terminal of inverter amplifier 119 and to a first terminal of transistor 127. The output terminal of inverter amplifier 119 is coupled to an input terminal of inverter amplifier 121 and to a first terminal of transistor 124. The output terminal of inverter amplifier 121 is coupled to an input terminal of pass gate transistor 117. The second terminal of transistor 127 is coupled to a first terminal of transistor 125 and to a first terminal of NOR gate 131. A first terminal of transistor 124 is coupled to a first terminal of transistor 123 and to a first terminal of NOR gate 129. An output terminal of NOR gate 129 is coupled to a second input terminal of NOR gate 131 and is coupled through resistor 135 to the gate terminal of n-channel transistor 133 and a first terminal of transistor 132. The output terminal of NOR gate 131 is coupled to a second input terminal of NOR gate 129 and to a gate terminal of n-channel transistor 139. A first terminal of transistor 139 is coupled to the common potential, while a second terminal of transistor 139 is coupled through resistor 137 to the output terminal of the buffer circuit, to a second terminal of transistor 132 and to a first terminal of transistor 133. The second terminal of transistor 133 is coupled to the Vex terminal. The Vpp terminal is coupled to the power terminal of NOR gate 131, to the power terminal of NOR gate 129, to a second terminal of transistor 125, to the second terminal of transistor 123, to the second terminal of transistor 107 and to the second terminal of transistor 105. The three buffer amplifiers which are added to the initial single amplifier have the same schematic diagram. The differences are that the WOFX4 signal is used in place of The WOE3.sub.-- signal and the IOPRBN(N=0-2) replaces the IOMUX3 signal. This buffer circuit receives an input signal IOMUX3 (or IOPRBN), buffers the signal, and applies the buffered signal to DQ3 (DQN) terminal.
Referring next to FIG. 2, a buffer supply circuit according to the prior art is shown. The input VPATDEN signal is coupled to an input terminal of inverting amplifier, to a first input terminal of NOR gate 211, and to a first input terminal of NAND gate 209. The output terminal of inverting amplifier 201 is coupled through delay line 203 to an input terminal of delay line 205 and to an input terminal of inverting amplifier 215. The output terminal of delay line 205 is coupled through inverting amplifier 207 to a second input terminal of AND gate 209 and to a second input terminal of NOR gate 211. The output terminal of NOR gate 211 is coupled to the substrate through equivalent diode 227 and to a first terminal of capacitor 213. The second terminal of capacitor 213 is coupled through diode-coupled n-channel transistor 231 to the Vs terminal, to the gate and a first terminal of n-channel transistor 237, to a gate of n-channel transistor 239, and to a gate terminal of n-channel transistor 225. A second terminal of transistor 237 is coupled to a first terminal and a gate of n-channel transistor 235. A second terminal of transistor 235 is coupled to a gate and a first terminal of n-channel transistor 233. A second terminal of transistor 233 is coupled to the Vs terminal. The output terminal of inverting amplifier 219 is coupled to the substrate by equivalent diode 221 and to a first terminal of capacitor 223. The output terminal of inverting amplifier 215 is coupled through inverting amplifier 217 to a gate terminal of n-channel transistor 241 and to a gate terminal of p-channel transistor 243. A first terminal of transistor 241 is coupled to ground, while a second terminal of transistor 241 is coupled to a first terminal of transistor 243, to a first terminal of capacitor 245 and to the substrate through equivalent diode 229. A second terminal of transistor 243 is coupled to the Vs terminal. A second terminal of capacitor 223 is coupled to a first terminal of transistor 225, to a first terminal of n-channel transistor 249, and to a gate terminal of transistor 247. A second terminal of transistor 225 is coupled to the Vs terminal. A second terminal of capacitor 245 is coupled to a first terminal of transistor 239, to a first terminal of transistor 247, and to a second terminal of transistor 249. A second terminal of transistor 239 is coupled to the Vs terminal. the second terminal of transistor 247 and the gate terminal of transistor 249 are coupled to the Vpp terminal.
The operation of the buffer supply unit of FIG. 2 can be understood as follows. When the output terminal of NOR gate 211 is low, the diode coupled transistor charges the node of the circuit which includes the gate terminal of transistor 239. When, in response to a change in the VPATDEN signal, the output terminal of NOR gate 211 is driven high, the increase in voltage at the gate terminal of transistor 239 causes transistor 239 to become conducting and the pump capacitor 245 is precharged. When, in response to a change in the UPATDEN signal, the output terminal of NOR gate 211 is driven low, the conduction of transistor 239 ceases because of the change in the voltage at the gate terminal of transistor 239. As before, when the output terminal of NOR gate 211 is low, the circuit node which includes the gate terminal of transistor 239 begins to charge. When the output terminal of NOR gate 211 is driven low, the node wherein transistor 241 and 243 are coupled is driven high (i.e., in response to a change in the UPATDEN signal). Simultaneously, with the high state of the transistor 241/245 node, the output terminal of inverting amplifier 219 is driven high, causing the pass transistor 247 to become conducting. The combination of conduction of the pass transistor 247 and the high state of the transistor 241/243 node causes charge to flow from the capacitor to the Vpp terminal. When the VPATDEN signal causes the NOR gate to be in a high state, capacitor 245 is once again is precharged. The change in the state of the VPATDEN signal results in a change in the state of the output terminal of inverting amplifier 219 causing transistor 247 to stop conduction. The change in state of the UPATDEN signal causes the transistor 241/243 node to be in a low state assisting the precharging of capacitor 245.
In the prior art, the solution to the problem of a variable configuration, discussed previously, requires different Vpp voltage levels for the one output buffer and the four output buffer configuration as well as an unnecessarily high power consumption for the one output buffer configuration. A need has therefore been felt for apparatus and an associated technique which provides a pumping capacitor not requiring different power supply levels for the one output buffer and the four output buffer configurations and which does not require unnecessary power for activating the one output buffer configuration.